rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3307 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 high accuracy anycap? 100 ma low dropout linear regulator functional block diagram thermal protection driver g m cc in adp3307 out r1 r2 nr gnd q1 err sd bandgap ref q2 v out = +3.3v v in + C adp3307-3.3 nr out err on off sd gnd r1 330k v in e out c2 0.47 m f c1 0.47 m f figure 1. typical application circuit features 0.8% accuracy over line and load regulations @ +25 8 c ultralow dropout voltage: 120 mv typical @ 100 ma requires only c o = 0.47 m f for stability anycap = stable with all types of output capacitors (including mlcc) current and thermal limiting low noise dropout detector low shutdown current: 1 m a 3.0 v to 12 v supply range C20 8 c to +85 8 c ambient temperature range several fixed voltage options ultrasmall sot-23-6 (rt-6) package excellent line and load regulations applications cellular telephones notebook, palmtop computers battery powered systems pcmcia regulator bar code scanners camcorders, cameras general description the adp3307 is a member of the adp330x family of precision low dropout anycap voltage regulators. the adp3307 stands out from the conventional ldos with a novel architecture and an enhanced process. its patented design requires only a 0.47 m f output capacitor for stability. this device is stable with any type of capacitor regardless of its esr (equivalent series resistance) value, including ceramic types (mlcc) for space restricted applications. the adp3307 achieves exceptional accuracy of 0.8% at room temperature and 1.4% overall accuracy over temperature, line and load regulations. the dropout voltage of the adp3307 is only 120 mv (typical) at 100 ma. the adp3307 operates with a wide input voltage range from 3.0 v to 12 v and delivers a load current in excess of 100 ma. it features an error flag that signals when the device is about to lose regulation or when the short circuit or thermal overload protection is activated. other features include shutdown and optional noise reduction capabilities. the adp330x anycap ldo family offers a wide range of output voltages and output current levels from 50 ma to 300 ma: adp3300 (50 ma, sot-6) adp3307 (100 ma, sot) adp3301 (100 ma, so-8) adp3302 (100 ma, dual output) adp3303 (200 ma) adp3306 (300 ma) anycap is a trademark of analog devices, inc.
C2C rev. 0 adp3307Cspecifications (@ t a = C20 8 c to +85 8 c, v in = 7 v, c in = 0.47 m f, c out = 0.47 m f, unless otherwise noted) 1 the following specifications apply to all voltage options. parameter symbol conditions min typ max units output voltage accuracy v out v in = v outnom + 0.3 v to 12 v i l = 0.1 ma to 100 ma t a = +25 c C0.8 +0.8 % v in = v outnom + 0.3 v to 12 v i l = 0.1 ma to 100 ma C1.4 +1.4 % line regulation v in = v outnom + 0.3 v to 12 v t a = +25 c 0.02 mv/v load regulation i l = 0.1 ma to 100 ma t a = +25 c 0.06 mv/ma ground current i gnd i l = 100 ma 0.76 2.0 ma i l = 0.1 ma 0.19 0.3 ma ground current in dropout i gnd v in = 2.5 v i l = 0.1 ma 0.6 1.2 ma dropout voltage v drop v out = 98% of v outnom i l = 100 ma 0.126 0.22 v i l = 10 ma 0.025 0.07 v i l = 1 ma 0.004 0.015 v shutdown threshold v thsd on 2.0 0.75 v off 0.75 0.3 v shutdown pin input current i sdin 0 < v sd , < 5 v 1 m a 5 < v sd 12 v @ v in = 12 v 22 m a ground current in shutdown i q v sd = 0 v, v in = 12 v mode t a = +25 c 0.005 1 m a v sd = 0 v, v in = 12 v t a = +85 c 0.01 3 m a output current in shutdown i osd t a = +25 c @ v in = 12 v 2 m a mode t a = +85 c @ v in = 12 v 4 m a error pin output leakage i el v eo = 5 v 13 m a error pin output low voltage v eol i sink = 400 m a 0.12 0.3 v peak load current i ldpk v in = v outnom + 1 v 170 ma output noise @ 3.3 v output v noise f = 10 hzC100 khz c nr = 0 100 m v rms c nr = 10 nf, c l = 10 m f30 m v rms notes 1 ambient temperature of +85 c corresponds to a junction temperature of 125 c under typical full load test conditions. specifications subject to change without notice. d v o d v in d v o d i l
adp3307 C3C rev. 0 absolute maximum ratings* input supply voltage . . . . . . . . . . . . . . . . . . . C0.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . C0.3 v to +16 v error flag output voltage . . . . . . . . . . . . . . . C0.3 v to +16 v noise bypass pin voltage . . . . . . . . . . . . . . . . C0.3 v to +5 v power dissipation . . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . C55 c to +125 c operating junction temperature range . . . C55 c to +125 c q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 c/w storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 s) . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ordering guide output package marking model voltage option code adp3307art-2.7 2.7 v rt-6 ltc adp3307art-3 3.0 v rt-6 luc adp3307art-3.2 3.2 v rt-6 lvc adp3307art-3.3 3.3 v rt-6 lwc contact the factory for the availability of other output voltage options. other members of anycap family 1 output package model current options 2 comments adp3300 50 ma sot-23-6 high accuracy adp3301 100 ma so-8 high accuracy adp3302 100 ma so-8 dual output adp3303 200 ma so-8 high accuracy adp3306 300 ma so-8, tssop-14 high accuracy, high current notes 1 see individual data sheets for detailed ordering information. 2 so = small outline, sot-23 = surface mount, tssop = thin shrink small outline. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3307 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function descriptions pin name function 1 gnd ground pin. 2 nr noise reduction pin. used for further reduc- tion of the output noise. (see text for details.) no connection if not used. 3 sd active low shutdown pin. connect to ground to disable the regulator output. when shut- down is not used, this pin should be con- nected to the input pin. 4 out output of the regulator, fixed 2.7 v, 3.0 v, 3.2 v or 3.3 v output voltage. bypass to ground with a 0.47 m f or larger capacitor. 5 in regulator input. 6 err open collector output that goes low to indi- cate that the output is about to go out of regulation. pin configuration top view (not to scale) 6 5 4 1 2 3 gnd nr sd err in out adp3307 warning! esd sensitive device
adp3307 C4C rev. 0 input voltage C volts output voltage C volts 3.202 3.198 3.195 3.3 4 14 5678910111213 3.201 3.200 3.197 3.196 3.199 v out = 3.2v i l = 0ma i l = 10ma i l = 100ma i l = 50ma figure 2. line regulation output voltage vs. supply voltage output load C ma ground current C m a 900 750 150 0 25 100 50 75 600 450 300 i l = 0 to 100ma figure 5. ground current vs. load current output load C ma input/output voltage C mv 120 96 0 0 25 100 50 75 72 48 24 figure 8. dropout voltage vs. output current Ctypical performance characteristics output load C ma output voltage C volts 3.202 3.195 0 10 100 20 30 40 50 60 70 80 90 3.201 3.200 3.199 3.198 3.197 3.196 v out = 3.2v v in = 7v figure 3. output voltage vs. load current up to 100 ma 0.2 C0.4 C45 C25 135 C5 15 35 75 95 115 55 0.1 0.0 C0.1 C0.2 C0.3 i l = 50ma i l = 0 i l = 100ma temperature C 8 c output voltage C % figure 6. output voltage variation % vs. temperature 5 4 0 01 0 234321 3 2 1 v out = 3.2v r l = 32 v input/output voltage C volts input voltage C volts figure 9. power-up/power-down input voltage C volts ground current C m a 800 640 0 0 1.2 12.0 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 480 320 160 v out = 3.2v i l = 0 figure 4. quiescent current vs. sup- ply voltage3.2 v (both outputs) temperature C 8 c ground current C m a 1000 800 0 C25 C5 135 15 35 55 75 95 115 600 400 200 figure 7. quiescent current vs. temperature time C m s input/output voltage C volts 8.0 5.0 0 0 20 200 40 60 80 100 120 140 160 180 7.0 6.0 3.0 1.0 4.0 2.0 v sd = v in c l = 0.47 m f r l = 32 v v out = 3.2v v in v out figure 10. power-up overshoot
adp3307 C5C rev. 0 volts 3.220 3.190 0 40 400 80 120 160 200 240 280 320 360 3.210 3.200 7.0 3.180 7.5 v out = 3.2v r l = 32 v c l = 0.47 m f v in time C m s figure 11. line transient response 3.220 3.210 0 100 500 200 300 400 3.190 3.180 100 10 3.200 volts ma time C m s v out = 3.2v c l = 4.7 m f figure 14. load transient volts 4 3 010 50 20 30 40 1 0 3 0 2 time C m s v sd c l = 0.47 m f v out = 3.2v r l = 32 v 3.2v figure 17. turn off time C m s volts 3.220 3.190 0 20 200 40 60 80 100 120 140 160 180 3.210 3.200 7.0 3.180 7.5 v out = 3.2v r l = 3.2k v c l = 0.47 m f v in figure 12. line transient response v out = 3.2v ma 300 200 01 5 234 0 4 2 0 100 volts v out i out time C sec 0.5 4.5 1.5 2.5 3.5 figure 15. short circuit current frequency C hz ripple rejection C db 10 100 10m 1k 10k 1m 0 C10 C100 C20 C30 C40 C50 C60 C70 100k a. 0.47 m f, r l = 33k v b. 0.47 m f, r l = 33 v c. 10 m f, r l = 33k v d. 10 m f, r l = 33 v v out = 3.3v d c b a C80 C90 d b c a figure 18. power supply ripple rejection 3.220 3.210 0 100 500 200 300 400 3.190 3.180 100 10 3.200 volts ma time C m s v out = 3.2v c l = 0.47 m f figure 13. load transient volts 4 3 0 0 20 100 40 60 80 2 1 0 3 v sd c l = 0.47 m f v out 3.2v c l = 4.7 m f v out = 3.2v r l = 32 v 3v time C m s figure 16. turn on 10 1 0.01 100 1k 100k 10k 0.1 frequency C hz voltage noise spectral density C m v hz v out = 5v, c l = 0.47 m f i l = 1ma, c nr = 0 v out = 2.7C 5.0v, c l = 4.7 m f i l = 1ma, c nr = 10nf v out = 2.7C 5.0v, c l = 0.47 m f i l = 1ma, c nr = 10nf v out = 3.3v, c l = 0.47 m f i l = 1ma, c nr = 0 0.47 m f bypass pin 5 to pin 1 figure 19. output noise density
adp3307 C6C rev. 0 theory of operation the adp3307 anycap ldo uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 which is varied to provide the available output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. ptat v os g m noninverting wideband driver input q1 adp3307 compensation capacitor attenuation (v bandgap /v out ) r1 d1 r2 r3 r4 output ptat current r load c load (a) gnd figure 20. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input offset volt- age that is repeatable and very well controlled. the gained up temperature proportional offset voltage is combined with the diode voltage to form a virtual bandgap voltage, implicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the trade-off of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. although the r1, r2 resistor divider is loaded by the diode d1, and a second divider consist- ing of r3 and r4, the values are chosen to produce a tempera- ture stable output. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and esr of the load capacitance. most ldos place strict requirements on the range of esr val- ues for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. moreover, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. these esr limitations make designing with conventional ldos more difficult because of their unclear specifications and the depen- dence of esr over temperature. this is no longer true with the adp3307 anycap ldo. it can be used with virtually any good quality capacitor, with no con- straint on the minimum esr. the innovative design allows the circuit to be stable with just a small 0.47 m f capacitor on the output. additional advantages of the design scheme include superior line noise rejection and very high regulator gain that lead to excellent line and load regulation. an impressive 1.4% accuracy is guaranteed over line, load and temperature. additional features of the circuit include current limit, thermal shutdown and noise reduction. compared to the standard solu- tions that give warning after the output has lost regulation, the adp3307 provides improved system performance by enabling the err pin to give warning before the device loses regulation. as the chips temperature rises above 165 c, the circuit acti- vates a soft thermal shutdown, indicated by a signal low on the err pin, to reduce the current to a safe level. to reduce the noise gain of the loop, the node of the main di- vider network (a) is made available at the noise reduction (nr) pin which can be bypassed with a small capacitor (10 nfC100 nf). application information capacitor selection: anycap output capacitors: as with any micropower device, output transient response is a function of the output capacitance. the adp3307 is stable with a wide range of capacitor values, types and esr (anycap). a capacitor as low as 0.47 m f is all that is needed for stability. however, larger capacitors can be used if high output current surges are anticipated. there is an upper limit on the size of the output capacitor. the adp3307 is stable with extremely low esr capacitors (esr ? 0), such as multi- layer ceramic capacitors (mlcc) or oscon. input bypass capacitor: an input bypass capacitor is not re- quired; however, for applications where the input source is high impedance or far from the input pins, a bypass capacitor is recommended. connecting a 0.47 m f capacitor from the input to ground reduces the circuits sensitivity to pc board layout. if a bigger output capacitor is used, the input capacitor should be 1 m f minimum. noise reduction a noise reduction capacitor (c nr ) can be used to further reduce the noise by 6 dbC10 db (figure 21). low leakage capacitors in 10 nfC100 nf range provide the best performance. as the noise reduction capacitor increases the high frequency loop-gain of the regulator, the circuit requires a larger output capacitor if it is used. the recommended value is 4.7 m f, as shown in figure 21. since the noise reduction pin (nr) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pick up from external sources. the pad connected to this pin should be as small as possible. long pc board traces are not recommended.
adp3307 C7C rev. 0 v out = 3.3v v in + c1 1 m f adp3307-3.3 nr out err on off sd gnd 330k in e out c2 4.7 m f + r1 c nr 10nf figure 21. noise reduction circuit thermal overload protection the adp3307 is protected against damage due to excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165 c. un- der extreme conditions (i.e., high ambient temperature and power dissipation), where die temperature starts to rise above 165 c, the output current is reduced until the die temperature has dropped to a safe level. output current is restored when the die temperature is reduced. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 125 c. calculating junction temperature device power dissipation is calculated as follows: p d = ( v in C v out ) i load + ( v in ) i gnd where i load and i gnd are load current and ground current, v in and v out are input and output voltages respectively. assuming i load = 100 ma, i gnd = 2 ma, v in = 5.5 v and v out = 3.3 v, device power dissipation is: p d = (5.5 C 3.3) 0.1 + 5.5 2 ma = 0.231 w d t = t j C t a = p d q j a = 0.231 165 = 38 c with a maximum junction temperature of 125 c, this yields a maximum ambient temperature of ~72 c. printed circuit board layout consideration surface mount components rely on the conductive traces or pads to transfer heat away from the device. appropriate pc board layout techniques should be used to remove heat from the immediate vicinity of the package. the following general guidelines will be helpful when designing a board layout: 1. pc board traces with larger cross section areas will remove more heat. for optimum results, use pc boards with thicker copper and wider traces. 2. increase the surface area exposed to open air so heat can be removed by convection or forced air flow. 3. do not use solder mask or silkscreen on the heat dissipating traces because it will increase the junction-to-ambient ther- mal resistance of the package. shutdown mode applying a ttl high signal to the shutdown pin or tying it to the input pin will turn the output on. pulling the shutdown pin down to a ttl low level or tying it to ground will turn the output off. in shutdown mode, quiescent current is reduced to less than 1 m a. error flag dropout detector the adp3307 will maintain its output voltage over a wide range of load, input voltage and temperature conditions. if the output is about to lose regulation, for example, by reducing the supply voltage below the combined regulated output and drop- out voltages, the err pin will be activated. the err output is an open collector that will be driven low. once set, the err or flags hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. applications circuits crossover switch the circuit in figure 22 shows that two adp3307s can be used to form a mixed supply voltage system. the output switches between two different levels selected by an external digital input. output voltages can be any combination of voltages from the ordering guide of the data sheet. adp3307-2.7 adp3307-3.3 + out in sd gnd + in out sd gnd c1 1.0 m f c2 0.47 m f v out = 2.7v/3.3v v in = 4v to 12v output select 4v 0v figure 22. crossover switch higher output current the adp3307 can source up to 100 ma without any heatsink or pass transistor. if higher current is needed, an appropriate pass transistor can be used, as in figure 23, to increase the output current to 1 a. adp3307-3.3 out in sd gnd + v in = 4v to 8v mje253* v out = 3.3v@1a c1 47 m f c2 10 m f *aavid531002 heat sink is used err r1 50 v figure 23. high output current linear regulator
adp3307 C8C rev. 0 outline dimensions dimensions shown in inches and (mm). c3234C8C12/97 printed in u.s.a. + v in = 2.5v to 3.5v c1 100 m f 10v l1 6.8 m h d1 1n5817 c2 100 m f 10v i lim v in sw1 sw2 gnd fb adp3000-adj r1 120 v r2 30.1k v 1% q1 2n3906 adp3307-3.3 in out gnd sd r3 124k v 1% r4 274k v q2 2n3906 c3 2.2 m f 3.3v@100ma figure 24. constant dropout post regulator 6-lead plastic surface mount (rt-6) 0.122 (3.10) 0.106 (2.70) pin 1 0.071 (1.80) 0.059 (1.50) 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.059 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) constant dropout post regulator the circuit in figure 24 provides high precision with low drop- out for any regulated output voltage. it significantly reduces the ripple from a switching regulator while providing a constant dropout voltage, which limits the power dissipation of the ldo to 30 mw. the adp3000 used in this circuit is a switching regulator in the step-up configuration.
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